The invention relates to electronic semiconductor devices and integrated circuits, and more particularly to fabrication methods of MOS and bipolar transistors in integrated circuits.
In the fabrication of semiconductor devices, it is well known that parasitic capacitances tend to decrease the operating speed of the devices. Accordingly, the industry is constantly attempting to decrease parasitic capacitance to obtain the concomitant increase in device operating speed.
Such parasitic capacitances arise whenever there are two charge carrying locations in the device or between the device and an external location separated by a dielectric. With the continued miniaturization of semiconductor devices, the distances between these charge carrying locations decreases and the thicknesses of the dielectrics also decreases, thereby increasing the parasitic capacitnace within the device being fabricated. Also, the doping levels have been increasing, this also leading to an increase in capacitance.